1. Field of the Invention
The present invention relates to a semiconductor device which realizes reduction in a device size and prevents an operation of a parasitic transistor, and a manufacturing method thereof.
2. Description of the Related Art
In a conventional semiconductor device, an N type drain well region and a P type back gate region are formed on a surface of a silicon substrate. Moreover, in the drain well region, a high-concentration N type drain region is formed. Meanwhile, in the back gate region, an N type source region is formed. On the surface of the silicon substrate between the drain region and the source region, a gate electrode is formed. Furthermore, in the back gate region, a P type diffusion layer connected to a source electrode is formed. Thus, an N-channel MOSFET is formed. By use of this structure, the back gate region and the source region are maintained to have the same potential. Thus, an operation of a parasitic NPN transistor is suppressed. This technology is described for instance in Japanese Patent Application Publication No. 2001-119019, pp. 6 to 7 and FIGS. 1 to 3.
In a conventional method for manufacturing a semiconductor device, an N type diffusion layer used as a drain region, a P type diffusion layer used as a back gate region, and an N type diffusion layer used as a source region are formed by ion implantation after an oxide film is formed on a substrate surface in a MOSFET formation region. Thereafter, depending on the need, in the P type diffusion layer used as the back gate region and the N type diffusion layer used as the source region, a P type diffusion layer connected to the source electrode are formed by ion implantation. Subsequently, the source electrode is formed so as to be connected to the N type diffusion layer used as the source region and the P type diffusion layer used as the back gate region. As a result, the P type diffusion layer used as the back gate region and the N type diffusion layer used as the source region are set to have the same potential. Thus, the operation of the parasitic NPN transistor is suppressed. This technology is described for instance in Japanese Patent Application Publication No. Hei 9 (1997)-139438, pp. 5 to 6 and FIGS. 4 to 6.
As described above, in the conventional semiconductor device, a contact hole for the source electrode is formed after the source region and the P type diffusion layer which suppresses the operation of the parasitic transistor are formed in the back gate region. Thus, the source electrode is connected to the P type diffusion layer and the source region through the contact hole. By use of this structure, when the contact hole is formed, mask misalignment at the time of formation of the P type diffusion layer and mask misalignment at the time of formation of the contact hole are taken into consideration. Thus, a width of the contact hole is increased. As a result, there is a problem that it is difficult to reduce a device size.
Moreover, in the conventional semiconductor device, the P type diffusion layer is formed in the back gate region in order to suppress the operation of the parasitic NPN transistor in the N-channel MOSFET device. However, since the P type diffusion layer is formed by a thermal diffusion step, a formation region in a deep portion of the back gate region is reduced. By use of this structure, there is a problem that it is difficult to reduce a resistance value in the deep portion of the back gate region and to suppress the operation of the parasitic NPN transistor. Meanwhile, in the case where the P type diffusion layer is formed across a large area in the deep portion of the back gate region, thermal diffusion time is increased. Thus, it is required to take account of lateral diffusion. In this case, there is a problem that the device size is increased more than necessary.
Furthermore, in the conventional method for manufacturing the semiconductor device, the P type diffusion layer is formed in the back gate region in order to suppress the operation of the parasitic NPN transistor in the N-channel MOSFET device. In this event, in order to reduce a resistance value of the back gate region and to reduce a base resistance value of the parasitic NPN transistor, a P type diffusion layer having a high impurity concentration is formed. However, mask misalignment at the time of formation of the P type diffusion layer may cause the P type diffusion layer to be formed in a region where a channel is formed below the gate electrode. In this case, the operation of the parasitic NPN transistor can be suppressed. However, there is a problem that a threshold (Vth) of the MOSFET is modulated.
In addition, in the conventional method for manufacturing the semiconductor device, after the back gate region of the MOSFET is formed in the silicon substrate and the source region and the P type diffusion layers of the MOSFET are formed in the back gate region of the silicon substrate, an insulating layer is formed on the silicon substrate. Subsequently, after contact holes are formed in the insulating layer by use of a heretofore known photolithography technology, the source electrode and the like are formed. By use of this manufacturing method, when the contact hole for the source electrode is formed, it is required to take account of mask misalignment at the time of formation of the P type diffusion layers in addition to mask misalignment with respect to the P type diffusion layers. For this reason, the width of the contact hole for the source electrode is increased. As a result, there is a problem that it is difficult to reduce the device size.